M_CAN

The M_CAN is a CAN IP module that can be realized as a stand-alone device, as part of an ASIC, or as a FPGA. The M_CAN performs communication according to ISO 11898-1 (identical to Bosch CAN specification 2.0 parts A and B). For connection to the physical layer additional transceiver hardware is required.

The message storage is intended to be a single- or dual-ported Message RAM outside of the module. It is connected to the M_CAN via the Generic Master Interface. Depending on the chosen integration, multiple M_CAN controllers can share the same Message RAM. The Host CPU is connected via the 32-bit Generic Slave Interface.

For reception up to 64 Rx Buffers and two Rx FIFOs for storage of up 64 messages each can be setup. Acceptance filtering is implemented by a combination of up to 128 filter elements whereas each one can be configured as a range, as a bit mask, or as a dedicated ID filter. For transmission 32 Tx Buffers are available. They can be configured as dedicated Tx Buffers, as part of a Tx FIFO, or as part of a Tx Queue. A Tx Event FIFO stores time stamp and identifier of transmitted messages.

For Altera FPGAs the Altera Avalon bus interface is provided, for Lattice FPGAs the Wishbone interface. They can easily be replaced by a user-defined module interface.